Coupled simulation to determine the impact of across wafer variations in oxide PECVD on electrical and reliability parameters of through-silicon vias
نویسندگان
چکیده
We demonstrate a coupled equipmentand feature-scale process simulation and its application to plasma-enhanced chemical vapor deposition (PECVD) as part of a sequence for the fabrication of a through-silicon via (TSV) interconnect. The TSV structure is characterized electrically and mechanically by means of finite element simulation. This chain allows one to determine the effects of process variations on the electrical and reliability characteristics of the TSV. The simulations predict an across wafer variation of the parasitic DC capacitance between the tungsten metallization and the silicon substrate of about 3%. However, mechanical simulations indicate only a minor influence of the oxide layer thickness variation on the reliability performance of the TSV. 2014 Elsevier B.V. All rights reserved.
منابع مشابه
Coupled Simulation to Determine Across Wafer Variations for Electrical and Reliability Parameters of Through-Silicon Vias
Three-dimensional (3D) integration of integrated circuits is a key challenge for the future evolution of semiconductor systems. Through silicon vias (TSV) are an integral component for interconnecting stacked circuits. For the fabrication of TSVs, a sequence of processing steps is required, including etching and deposition. Inevitable variations, for instance across the wafer or due to fluctuat...
متن کاملImpact of Silicon Wafer Orientation on the Performance of Metal Source/Drain MOSFET in Nanoscale Regime: a Numerical Study
A comprehensive study of Schottky barrier MOSFET (SBMOSFET) scaling issue is performed to determine the role of wafer orientation and structural parameters on the performance of this device within Non-equilibrium Green's Function formalism. Quantum confinement increases the effective Schottky barrier height (SBH). (100) orientation provides lower effective Schottky barrier height in compa...
متن کاملAnalytical Threshold Voltage Computations for 22 nm Silicon-on-Diamond MOSFET Incorporating a Second Oxide Layer
In this paper, for the first time, an analytical equation for threshold voltage computations in silicon-on-diamond MOSFET with an additional insulation layer is presented; In this structure, the first insulating layer is diamond which covered the silicon substrate and second insulating layer is SiO2 which is on the diamond and it is limited to the source and drain on both sides. Analytical solu...
متن کاملImprovement of a Nano-scale Silicon on Insulator Field Effect Transistor Performance using Electrode, Doping and Buried Oxide Engineering
In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a silicon region has embedded in the buried oxide. In order to reduce th...
متن کاملImplementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration
This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si–glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructu...
متن کامل